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Content Provider | IEEE Xplore Digital Library |
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Author | Kirner, R. Puschner, P. |
Copyright Year | 2007 |
Description | Author affiliation: Inst. fur Technische Informatik, Technische Univ., Wien (Kirner, R.; Puschner, P.) |
Abstract | Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded software is generally increasing, it becomes more and more complex to verify the correct temporal behavior of software, running on this high-end embedded computer systems. To achieve time-predictability the authors introduced a very rigid software execution model with distribution being realized based on the time-triggered communication model. In this paper we analyze the time-predictability of a preempting task-activation, running on a hardware with direct-mapped instruction caches. As one result we analyze why a task-preemption driven by a clock interrupt is not suitable to guarantee time-predictability. As a second result, we present a time-predictable task-preemption driven by an instruction counter. |
Starting Page | 87 |
Ending Page | 93 |
File Size | 148968 |
Page Count | 7 |
File Format | |
ISBN | 0769527655 |
DOI | 10.1109/ISORC.2007.56 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2007-05-07 |
Publisher Place | Greece |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Real time systems Embedded system Hardware Timing Clocks Computer architecture Software performance Pipelines Embedded software Counting circuits |
Content Type | Text |
Resource Type | Article |
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