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Content Provider | IEEE Xplore Digital Library |
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Author | Goto, K. Oguma, T. Fukuoka, Y. |
Copyright Year | 1998 |
Description | Author affiliation: Toshiba Corp., Tokyo, Japan (Goto, K.) |
Abstract | The authors have developed the B/sup 2/it printed circuit board. The technology was reported initially in a paper at the IMC meeting in April 1996. Since that time, this technology has been applied to a variety of boards. Among these boards, we report in this paper the B/sup 2/it application to semiconductor packaging. The product has /spl phi/0.2/spl sim/0.1 mm bumps (fine bumps). In order to produce a multilayer high density printed circuit board, we need to add up each layer with conductive bumps over the base layer, which we call the en bloc laminate process. By repeating the en bloc laminate process multiple times, multilayers and stacked arrays are possible. Signals can go down to internal layers directly from surface pad via bumps. This is effective for substrates such as BGA type packages. With the use of the B/sup 2/it/sup TM/ method, it is possible to omit the outer layer plating process. This is an advantage for fine line patterning, because etching the copper foil alone enables circuit patterning. In addition, we introduced two types of liquid photoresist process: the ED method, and the spin coater liquid photoresist process. |
Starting Page | 316 |
Ending Page | 320 |
File Size | 817179 |
Page Count | 5 |
File Format | |
ISBN | 0780350901 |
DOI | 10.1109/IEMTIM.1998.704667 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1998-04-15 |
Publisher Place | Japan |
Access Restriction | Subscribed |
Rights Holder | Organizing Committee |
Subject Keyword | Printed circuits Wiring Laminates Printing Copper Dielectrics Substrates Packaging Resists Manufacturing processes |
Content Type | Text |
Resource Type | Article |
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