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Content Provider | IEEE Xplore Digital Library |
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Author | Chicha, Z. Milinkovic, L. Smiljanic, A. |
Copyright Year | 2011 |
Description | Author affiliation: Department of Telecommunications, School of Electrical Engineering, Belgrade University, Serbia (Chicha, Z.; Milinkovic, L.; Smiljanic, A.) |
Abstract | The pool of available IPv4 addresses is being depleted, comprising less than 10% of all IPv4 addresses. At the same time, the bit-rates at which packets are transmitted are increasing, and the IP lookup speed must be increased as well. Consequently, the IP lookup algorithms are in the research focus again because the existing solutions were designed for IPv4 addresses, and are not sufficiently scalable. In this paper, we compare FPGA implementations of the balanced parallelized frugal lookup (BPFL) algorithm, and the parallel optimized linear pipeline (POLP) lookup algorithm that efficiently use the memory, and achieve the highest speeds. |
Starting Page | 270 |
Ending Page | 275 |
File Size | 442657 |
Page Count | 6 |
File Format | |
ISBN | 9781424484546 |
e-ISBN | 9781424484560 |
e-ISBN | 9781424484553 |
DOI | 10.1109/HPSR.2011.5986037 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2011-07-04 |
Publisher Place | Spain |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Pipeline processing IP networks Search engines Field programmable gate arrays Memory management Pipelines System-on-a-chip FPGA Internet router IP lookup |
Content Type | Text |
Resource Type | Article |
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