NDLI: Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs

Content Provider	IEEE Xplore Digital Library
Author	Lines, A.
Copyright Year	2003
Description	Author affiliation: Fulcrum Microsystems, Calabasas, CA, USA (Lines, A.)
Abstract	Asynchronous circuits can provide an elegant and high performance interconnect solution for synchronous system-on-chip (SoC) designs with multiple clock domains. This 'globally asynchronous, locally synchronous' (GALS) approach simplifies global timing and synchronization problems, improving performance, reliability, and development time. Fulcrum Microsystems' SoC interconnect, 'Nexus', includes a 16 port, 36 bit asynchronous crossbar which connects via asynchronous channels to clock domain converters for each synchronous module. Each synchronous module has its own local clock domain, and can send a variable length burst of data to any other module. In TSMC's 130 nm LV low-K process, the system achieves 1.35 GHz at 1.2 V with less than 5 mm/sup 2/ area. Power scales linearly with bandwidth, from a few mW of leakage to 8 W at the peak 780 Gb/s cross-section bandwidth. Latency through the interconnect is 2 ns plus 1/2 to 2/3 clock cycles of the receiving module. This compares favorably with other SoC interconnect solutions that have less bandwidth, higher energy per transfer and longer latencies. Nexus is an innovative and comprehensive solution to the challenge of SoC interconnect.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Microprocessors & Microcomput
Starting Page	2
Ending Page	9
File Size	586663
Page Count	8
File Format	PDF
ISBN	076952012X
DOI	10.1109/CONECT.2003.1231470
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-08-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Clocks Integrated circuit interconnections Delay Timing Bandwidth Power system interconnection Asynchronous circuits Synchronization Chip scale packaging
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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