NDLI: MOS device structure development for ULSI: low power/high speed operation

Content Provider	IEEE Xplore Digital Library
Author	Woo-Hyeong Lee
Copyright Year	1995
Description	Author affiliation: Inter-Univ. Semiconductor Res. Center, Seoul Nat. Univ., South Korea (Woo-Hyeong Lee)
Abstract	The historical development of MOS structures was briefly reviewed and its trend also examined. On the basis of this consideration, the new MOS device structure, INSEC (I_n_trinsic S_ilicon E_pi-C_hannel) MOSFET was proposed for low power/high speed operation. The concept of the INSEC MOSFET is to reduce the subthreshold swing by introducing a thin intrinsic epitaxial silicon layer into the channel with a high impurity concentration. By this method, we can reduce the threshold voltage without any increase in the off-state leakage current and reduce the lateral electric field significantly. DIBL (drain-induced barrier lowering) can be suppressed successfully by controlling the channel impurity concentration below the intrinsic silicon epi-layer. The INSEC MOSFET can be operated with high performances even at the scaled supply voltage by controling its intrinsic epi-layer thickness.
Starting Page	607
Ending Page	612
File Size	539375
Page Count	6
File Format	PDF
ISBN	0780327861
DOI	10.1109/ICMEL.1995.500937
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-09-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOS devices Ultra large scale integration MOSFET circuits Silicon Impurities Power MOSFET Threshold voltage Leakage current Voltage control Thickness control
Content Type	Text
Resource Type	Article

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