NDLI: An efficient FPGA implementation of a wavelet coder/decoder

Content Provider	IEEE Xplore Digital Library
Author	Elghamery, N.A. Habib, S.E.-D.
Copyright Year	2000
Description	Author affiliation: Electron. Inst., Nat. Res. Centre, Giza, Egypt (Elghamery, N.A.)
Abstract	This paper presents an efficient VLSI architecture for the one-dimensional discrete wavelet transform (DWT). The VLSI architecture is described using VHDL and implemented on an Altera FLEX10 FPGA. The main features of the proposed architecture are: (1) no explicit downsampling block is used, and downsampling is effected using a multiclock scheme, rather than using a separate dedicated block for the decimation function; multiplierless implementation through the exclusive use of biorthogonal B-spline filters; Modular architecture that allows extension to an arbitrary number of decomposition levels by simply cascading a basic module. Simulation results show that the proposed coding and decoding scheme is capable of producing high quality reconstructed signals.
Starting Page	269
Ending Page	272
File Size	457110
Page Count	4
File Format	PDF
ISBN	9643600572
DOI	10.1109/ICM.2000.916458
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-31
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Decoding Discrete wavelet transforms Convolution Low pass filters Spline Very large scale integration Signal resolution Computer architecture Hardware
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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