NDLI: Critical charge model for transient latch-up in VLSI CMOS circuits

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Proceedings of the 2015 International Conference on Microelectronic Test Structures

2014 International Conference on Microelectronic Test Structures (ICMTS)

2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)

2012 IEEE International Conference on Microelectronic Test Structures

2011 IEEE ICMTS International Conference on Microelectronic Test Structures

2010 International Conference on Microelectronic Test Structures (ICMTS)

2009 IEEE International Conference on Microelectronic Test Structures

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International Conference on Microelectronic Test Structures, 2003.

Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.

ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153)

ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)

ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)

ICMTS 1998. Proceedings of 1998 International Conference on Microelectronic Test Structures (Cat. No.98CH36157)

1997 IEEE International Conference on Microelectronic Test Structures Proceedings

Proceedings of International Conference on Microelectronic Test Structures

Proceedings International Conference on Microelectronic Test Structures

Proceedings of 1994 IEEE International Conference on Microelectronic Test Structures

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

ICMTS 92 Proceedings of the 1992 International Conference on Microelectronic Test Structures

International Conference on Microelectronic Test Structures

Proceedings of the 1991 International Conference on Microelectronic Test Structures

Proceedings of the 1989 International Conference on Microelectronic Test Structures

Gate dimension characterization using the inversion layer

Off-line photolithographic parameter extraction using electrical test structures

Analysis of the determination of the dimensional offset of conducting layers and MOS transistors

A floating gate method for MOS transistor gate capacitance and Leff measurements and its implementation in a parametric test

High speed measurement of FET V/sub th/ at low I/sub d/

Parameter extraction for a SPICE II VDMOS model

Standardization of CMOS unit process development

The INMOS integrated parametric test and analysis system

Test masks for micromachining silicon

An expert system for process diagnosis (MOS product testing)

MOSFET effective dimensions determination for VLSI process evaluation

Subtleties of SPICE MOSFET parameter extraction

Full characterization of MOS transistors in CMOS technologies

Enhanced MOS parameter extraction and SPICE modelling for mixed analogue and digital circuit simulation

Area-periphery partitioning of currents in self-aligned silicon bipolar transistors

A fast measurement technique for the determination of small signal parameters of the bipolar transistor

Fault simulation for fault-tolerant multi-Mbit RAMs

Evaluation technique of gate oxide reliability with electrical and optical measurements

ICMTS 1989. Proceedings of the 1989 International Conference on Microelectronic Test Structures (Cat. No.89CH2693-0)

Effects of interface traps and bulk traps in SiO/sub 2/ on hot-carrier-induced degradation

MOSFET interface state densities of different technologies

Contact electromigration: a method to characterize test structures for reliability parameter estimation

Thermal conductivity measurements of thin-film silicon dioxide

An overlay vernier and process bias monitor measured by voltage contrast SEM

The effect of contact geometry on the value of contact resistivity extracted from Kelvin structures

Measurement of misalignment using a triangular MOS transistor

Test structure for evaluation of 1/f noise in CMOS technologies

Test structure for measurement of conductive film thickness

A new wafer surface charge monitor (CHARM)

Electrical characterization of minority carrier transport parameters in n-type heavily doped silicon

Design and implementation of channel mobility measurement modules

A simple test structure for measuring substrate resistivity

A new test structure for in-depth lifetime profiling of thin Si epitaxial layers

CMOS process uniformity evaluation through the characterisation of parasitic transistors

Standard error in die yield projections from defect test structures

Automating and sequencing C-V measurements for process fault diagnosis using a pattern-recognition approach (MOS test structure)

A neural network approach for classifying test structure results

Automatic parameter extraction system with process failure diagnostics for CMOS process

Statistical worst-case MOS parameter extraction

Analysis of intra-level isolation test structure data by multiple regression facilitate rule identification for diagnostic expert systems

A programmable-load CMOS ring oscillator/inverter chain for propagation-delay measurements

Inverter propagation delay measurements using timing sampler circuits

An experimental measurement technique of interconnection RC delay for integrated circuits using the step voltage response

An opamp as a tool for testing

Novel test structure to study location of breakdown for trench capacitor

Critical charge model for transient latch-up in VLSI CMOS circuits

Electrostatic discharge test structures for CMOS circuits

Drain and bulk symmetry factor: a statistical tool to improve device reliability

Proceedings of the IEEE International Conference on Microelectronic Test Structures

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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