NDLI: "Flea-flicker" multipass pipelining: an alternative to the high-power out-of-order offense

Content Provider	IEEE Xplore Digital Library
Author	Barnes, R.D. Ryoo, S. Hwu, W.W.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA (Barnes, R.D.)
Abstract	As microprocessor designs become increasingly power-and complexity-conscious, future microarchitectures must decrease their reliance on expensive dynamic scheduling structures. While compilers have generally proven adept at planning useful static instruction-level parallelism, relying solely on the compiler's instruction execution arrangement performs poorly when cache misses occur, because variable latency is not well tolerated. This paper proposes a new micro architectural model, multipass pipelining, that exploits meticulous compile-time scheduling on simple in-order hardware while achieving excellent cache miss tolerance through persistent advance preexecution beyond otherwise stalled instructions. The pipeline systematically makes multiple passes through instructions that follow a stalled instruction. Each pass increases the speed and energy efficiency of the subsequent ones by preserving computed results. The concept of multiple passes and successive improvement of efficiency across passes in a single pipeline distinguishes multipass pipelining from other runahead schemes. Simulation results show that the multipass technique achieves 77% of the cycle reduction of aggressive out-of-order execution relative to in-order execution. In addition, micro architectural-level power simulation indicates that benefits of multipass are achieved at a fraction of the power overhead of full dynamic scheduling.
Starting Page	12
Ending Page	330
File Size	346821
Page Count	319
File Format	PDF
ISBN	0769524400
DOI	10.1109/MICRO.2005.1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-12
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Out of order Dynamic scheduling Microprocessors Microarchitecture Parallel processing Delay Processor scheduling Hardware Energy efficiency
Content Type	Text
Resource Type	Article

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