NDLI: On-line and off-line testable design of random access memories

Content Provider	IEEE Xplore Digital Library
Author	Subramanian, S. Lala, P.K.
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA (Subramanian, S.)
Abstract	The authors propose a testable design of random access memories (RAM) which facilitates both on-line and off-line testing of the devices. The high density of the memory devices necessitates high speed off-line testing techniques. Critical applications desire on-line testability of these devices. The proposed design partitions the chip into blocks and sets in order to achieve high speed off-line testability as well as on-line testability.
Starting Page	26
Ending Page	30
File Size	280369
Page Count	5
File Format	PDF
ISBN	0818641509
DOI	10.1109/MT.1993.263154
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-08-09
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Random access memory Decoding Logic testing Circuit testing Read-write memory Electrical fault detection Fault detection Logic devices Logic circuits
Content Type	Text
Resource Type	Article

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On-line and off-line testable design of random access memories