NDLI: A PLL for clock generation with automatic frequency control under TID effects

Content Provider	IEEE Xplore Digital Library
Author	Dallasen, R.V. Wirth, G.I. Both, T.H.
Copyright Year	2012
Description	Author affiliation: Departament of Electrical Engineering, Federal University of Rio Grande do Sul, Porto Alegre, Brazil (Dallasen, R.V.; Wirth, G.I.) \|\| Microelectronics Program (PGMICRO), Federal University of Rio Grande do Sul, Porto Alegre, Brazil (Both, T.H.)
Abstract	This paper presents a PLL scheme for clock generation with a Total Ionizing Dose (TID) degradation detector. Externally to the PLL circuitry, when the degradation due to TID effects reaches a certain predefined threshold, the circuit reduces the clock frequency output. To compensate for the increased delay caused by the total dose effect (TID), the system increases the clock period in order to avoid timing violations, increasing the chip lifespan. The circuit was designed in a 0.35µm CMOS process and simulated with HSPICE tool.
Starting Page	1
Ending Page	5
File Size	572223
Page Count	5
File Format	PDF
ISBN	9781467326063
e-ISBN	9781467326087
DOI	10.1109/SBCCI.2012.6344441
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-30
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage-controlled oscillators Voltage control Phase locked loops Clocks Degradation Charge pumps Phase frequency detector
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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A PLL for clock generation with automatic frequency control under TID effects