NDLI: Low-power dual V/sub th/ pseudo dual V/sub dd/ domino circuits

Content Provider	IEEE Xplore Digital Library
Author	Dhillon, Y.S. Diril, A.U. Chatterjee, A. Singh, A.D.
Copyright Year	2004
Description	Author affiliation: School of ECE, Georgia Tech., Atlanta, GA, USA (Dhillon, Y.S.)
Abstract	Domino logic is a commonly used alternative to CMOS logic for designing circuits with high speed and/or low area requirements. Although it provides higher speed and lower area, domino logic has relatively higher dynamic power consumption than CMOS logic due to a precharge/evaluate based operation. We propose a novel low-power domino gate design and also a methodology to use these low-power but slower gates with regular domino logic gates in combinational circuits to achieve low-power operation without changing the circuit delay. We apply our method on ISCAS'85 benchmark circuits and find that replacing the off-critical path normal domino gates with the proposed low-power gates reduces power consumption of the circuits by 20.6% on the average without affecting the circuit timing.
Sponsorship	Brazilian Comput. Soc. Brazilian Microelectronics Soc. ACM SIGDA IEEE CAS
Starting Page	273
Ending Page	277
File Size	331322
Page Count	5
File Format	PDF
ISBN	1581139470
DOI	10.1109/SBCCI.2004.240982
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-11
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	CMOS logic circuits Logic design Energy consumption Logic gates Delay Algorithm design and analysis Low voltage Combinational circuits MOS devices Capacitance
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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