NDLI: Some experiments in test pattern generation for FPGA-implemented combinational circuits

Content Provider	IEEE Xplore Digital Library
Author	Renovell, M. Portal, J.M. Faure, P. Figueras, J. Zorian, Y.
Copyright Year	2000
Description	Author affiliation: LIRMM-UM2, Montpellier, France (Renovell, M.)
Abstract	This paper studies the test pattern generation problem for FPGA implemented combinational circuits. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of manufacturing-oriented test procedure, application-oriented test procedure and AC-non-redundant fault. Then, the test pattern generation problem is discussed and it is pointed out that a high AC-non-redundant fault coverage can be obtained only by using an adequate FPGA representation. It is also shown that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.
Starting Page	3
Ending Page	8
File Size	473139
Page Count	6
File Format	PDF
ISBN	076950843X
DOI	10.1109/SBCCI.2000.876000
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-18
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Test pattern generators Combinational circuits Field programmable gate arrays Circuit testing Logic testing Manufacturing Programmable logic arrays Performance evaluation Circuit faults Life estimation
Content Type	Text
Resource Type	Article

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Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits

TOF: a tool for test pattern generation optimization of an FPGA application oriented test

A new functional fault model for FPGA application-oriented testing

A Test Pattern Generation Method Based on Fault Injection for Logic Elements of FPGA

Analyzing the test generation problem for an application-oriented test of FPGAs

Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs

Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays

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Some experiments in test pattern generation for FPGA-implemented combinational circuits

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