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  1. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.
  2. International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06)
  3. A Partial Irregular-Network Routing on Faulty k-ary n-cubes
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2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative architecture for future generation high-performance processors and systems (iwia 2007)
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06)
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems [Cover]
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems-Title
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems-Copyright
Message from the Editors
Reviewing Committee
A Holistic Approach to System Reliability in Blue Gene
Redundancy in Multi-core Memory-Rich Application-Specific PIM Chips
Improving Instruction Issue Bandwidth for Concurrent Error-Detecting Processors
The Speculative Prefetcher and Evaluator Processor for Pipelined Memory Hierarchies
Responsive Multithreaded Processor for Distributed Real-Time Processing
A Partial Irregular-Network Routing on Faulty k-ary n-cubes
Predictive Switching in 2-D Torus Routers
Hardware Support for MPI in DIMMnet-2 Network Interface
Compilation for Delay Impact Minimization in VLIW Embedded Systems
Real-Time Operating System Kernel for Multithreaded Processor
Author index
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
2001 Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)
Innovative Architecture for Future Generation High-Performance Processors and Systems
Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems

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A Partial Irregular-Network Routing on Faulty k-ary n-cubes

Content Provider IEEE Xplore Digital Library
Author Koibuchi, M. Yoshinaga, T. Nishimura, Y.
Copyright Year 2006
Description Author affiliation: National Inst. of Informatics (Koibuchi, M.)
Abstract Interconnection networks have been studied to connect a number of processing elements on parallel computers. Their design increasingly includes a challenge to high fault-tolerance, as entire systems become complicated. This paper presents a partial irregular-network routing in order to provide a high fault-tolerance in k-ary n-cube networks. Since an irregular-network routing usually performs poorly in k-ary n-cube networks, it is only used for progressive deadlock-recovery, and avoiding hard failures. The network is logically divided into the fault and regular regions. In the regular region, most packets are transferred along fully adaptive paths that are computed, assuming that there are no hard failures, so as to uniformly distribute the traffic. Simulation results show that the proposed routing achieves the same throughput as that of Duato's protocol under no hard failures. As the number of faulty links increases to up to 8 on 256 nodes, its throughput is only decreased by 15%. Moreover, the throughput of the proposed deadlock-recovery routing is almost maintained during a dynamic reconfiguration
Sponsorship IEEE CPS
Starting Page 57
Ending Page 64
File Size 471773
Page Count 8
File Format PDF
ISBN 0769526896
ISSN 15373223
DOI 10.1109/IWIAS.2006.23
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2006-01-23
Publisher Place USA
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Routing Throughput System recovery Multiprocessor interconnection networks Computer networks Concurrent computing Fault tolerant systems Fault tolerance Distributed computing Telecommunication traffic massively parallel computers Adaptive routing fault tolerance progressive deadlock recovery interconnection networks
Content Type Text
Resource Type Article
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