NDLI: A Multi-Cell Variable Frequency Interleaved ZCS Boost Rectifier Digitally Controlled by FPGA

Content Provider	IEEE Xplore Digital Library
Author	Canesin, C.A. Goncalves, F.A.S.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng., Sao Paulo Univ. (Canesin, C.A.; Goncalves, F.A.S.)
Abstract	This paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by field programmable gate array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400 V nominal output voltage and 220 $V_{rms}$ nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device
Starting Page	1382
Ending Page	1387
File Size	7068582
Page Count	6
File Format	PDF
ISBN	1424404967
DOI	10.1109/ISIE.2006.295674
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-09
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Zero current switching Rectifiers Digital control Field programmable gate arrays Electromagnetic interference Reactive power Diodes Voltage control Switches
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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