NDLI: Analysis and software implementation of a robust synchronizing circuit PLL circuit

Content Provider	IEEE Xplore Digital Library
Author	Costa Jr., D.R. Rolim, L.G.B. Aredes, M.
Copyright Year	2003
Description	Author affiliation: Cidade Univ., Rio de Janeiro, Brazil (Costa, D.R., Jr.; Rolim, L.G.B.; Aredes, M.)
Abstract	This paper presents the analysis and software implementation of a robust synchronizing circuit - PLL circuit - designed for using in the controller of active power line conditioners. The basic problem consists in designing a PLL circuit that can track accurately and continuously the positive-sequence component at the fundamental frequency and its phase angle, even when the system voltage of the bus, to which the active power line conditioner is connected, is distorted and/or unbalanced. The fundaments of the PLL circuit are discussed. It is shown that the PLL can fail in tracking the system voltage during the startup, under some adverse conditions. Moreover, it is shown that oscillations caused by the presence of sub-harmonics can be very critical and can pull the stable point of operation synchronized to that sub-harmonic frequency. Oscillations at the reference input are also discussed, and the solution of this problem is presented. Finally, experimental and simulation results are shown and compared.
Sponsorship	Ind. Electron. Soc. IEEE COPPE-Federal Univ. of Rio de Janeiro
Starting Page	292
Ending Page	297
File Size	527348
Page Count	6
File Format	PDF
ISBN	0780379128
DOI	10.1109/ISIE.2003.1267261
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-09
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Robustness Phase locked loops Frequency synchronization Phase detection Detectors Voltage-controlled oscillators Robust control Active filters Voltage
Content Type	Text
Resource Type	Article

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