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Author index

Proceedings The Seventh IEEE European Test Workshop

IEEE European Test Workshop, 2001.

Proceedings IEEE European Test Workshop

European Test Workshop 1999 (Cat. No.PR00390)

On path selection for delay fault testing considering operating conditions [logic IC testing]

Content Provider	IEEE Xplore Digital Library
Author	Seshadri, B. Pomeranz, I. Reddy, S.M. Kundu, S.
Copyright Year	2003
Description	Author affiliation: Electr. & Comput. Eng., Purdue Univ., W.Lafayette, IN, USA (Seshadri, B.; Pomeranz, I.)
Abstract	Path delays in deep submicron designs are sensitive to the operating point of the design, which is defined by the temperature and supply voltage. Moreover, a change in the operating conditions may affect different paths differently. We study a path selection technique for path delay fault test generation that takes into account possible variations in operating conditions. In developing the path selection procedure, we assume that the operating conditions are uniform across multiple gates, however, they are unknown and may assume one of a large range of values. The paths selected for test generation must include the critical paths for any operating point in this range. The study provides a quantitative analysis of path criticality at different operating conditions.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council (TTTC)
Starting Page	141
Ending Page	146
File Size	240468
Page Count	6
File Format	PDF
ISBN	0769519083
ISSN	15301877
DOI	10.1109/ETW.2003.1231681
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-05-28
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit testing Voltage Semiconductor process modeling Timing Delay effects Clocks Temperature sensors Semiconductor device testing Electrical fault detection
Content Type	Text
Resource Type	Article

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