NDLI: A novel FPGA design of modified residue to binary converter for three moduli set

Content Provider	IEEE Xplore Digital Library
Author	Senthilkumar, T. Prakash, G.
Copyright Year	2013
Description	Author affiliation: K.S.Rangasamy Coll. of Technol., Tiruchengode, India (Senthilkumar, T.; Prakash, G.)
Abstract	This paper proposes a novel modified reverse converter for the unrestricted moduli set. This uses to investigate the Residue Number System (RNS) to decimal equivalent binary conversion for the utilization of RNS numbers in Digital Signal Processing (DSP) applications. First, we simplify the Chinese Remainder Theorem in order to obtain a reverse converter that uses mod-(2n-1) operations. Next, we further analyze the theorem for the low complexity implementation that does not require the explicit use of modulo operation in the conversion process and we prove that theoretically speaking it outperforms state of the art equivalent converters. The proposed converter is implemented on Xilinx Spartan 3 field-programmable gate array. The results indicate that the proposal shows the better performance in conversion time, area cost and power consumption.
Sponsorship	IEEE Madras Sect. ED Chapter
Starting Page	1
Ending Page	4
File Size	724252
Page Count	4
File Format	PDF
ISBN	9781467353007
e-ISBN	9781467353014
DOI	10.1109/ICEVENT.2013.6496582
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FPGA Reverse conversion Chinese Remainder Theorem Residue arithmetic Indexes Residue Number System
Content Type	Text
Resource Type	Article

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