NDLI: Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research

Content Provider	IEEE Xplore Digital Library
Author	Ogawa, E. Matsuda, Y. Misono, T. Kobayashi, R. Kise, K.
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Sci., Tokyo Inst. of Technol., Tokyo, Japan (Ogawa, E.; Matsuda, Y.; Misono, T.; Kobayashi, R.; Kise, K.)
Abstract	In order to develop high performance computer systems efficiently, environments to evaluate architectural ideas are required. Software environments such as simulators are very flexible, and thus often used. On the other hand, if the target hardware is complex and large, it is very hard to finish the simulation in practical time because of software's slow simulation speed. Thus, we develop a hardware environment for efficient evaluation of computer systems. We propose and develop an IBM PC Compatible SoC on an FPGA where hardware developers can evaluate their custom architectures. The SoC has an x86 soft core processor which can run general purpose operating systems. By making the proposed system run on FPGAs of two major vendors, i.e. Xilinx and Altera, we believe that it can be widely adopted. Besides, the SoC can be used for learning computer systems, because of its open-source policy. In this paper, we detail the design and implementation of the proposed SoC, and verify that it accurately runs some applications. As a case study to demonstrate usability of the SoC for computer research, we implement two types of L2 caches in Verilog HDL and evaluate their performance by running the SPEC CPU2000 INT benchmark suite. Additionally, we discuss how the SoC can be used for computer education.
Starting Page	65
Ending Page	72
File Size	530144
Page Count	8
File Format	PDF
e-ISBN	9781479986705
DOI	10.1109/MCSoC.2015.35
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-23
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computers Reconfigurable-System FPGA Education Process control Random access memory SoC X86 Hardware IP networks Hardware design languages Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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