NDLI: Achieveing reduced area by Multi-bit Flip flop design

Content Provider	IEEE Xplore Digital Library
Author	Prakash, G. Sathishkumar, K. Sakthibharathi, B. Saravanan, S. Vijaysai, R.
Copyright Year	2013
Description	Author affiliation: VLSI Design, SASTRA Univ., Thanjavur, India (Prakash, G.; Sathishkumar, K.; Sakthibharathi, B.) \|\| SASTRA Univ., Thanjavur, India (Saravanan, S.; Vijaysai, R.)
Abstract	Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role on Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flipflop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop performance one of the promising way is to merge the clock pulse. The Multi-bit Flip-flop is designed by single clock pulse and achieves same functionality like two single-bit Flip-flop. A shift register is designed using both Single-Bit Flip-Flop (SBFF) and Multi-Bit Flip-Flop (MBFF). This paper analyzes the timing performance of both SBFF and MBFF in Xilinx Virtex-5 family (XC5VLX50). These results in favor of Multi-Bit Flip-Flop as reduction of Clock network such as clock buffer and gate delay.
Sponsorship	IEEE Madras Sect.
Starting Page	1
Ending Page	4
File Size	225464
Page Count	4
File Format	PDF
ISBN	9781467329064
e-ISBN	9781467329071
DOI	10.1109/ICCCI.2013.6466259
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches Single bit flip flop Flip-flop Delay Optimization Flip-flops Clock network Logic gates Latch Clock buffer Gate delay Multi bit flip flop Clocks
Content Type	Text
Resource Type	Article

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