NDLI: Model and measurements of a transmission line with integrated symmetrical 1-kV HBM broadband ESD Protection in advanced CMOS technologies

Content Provider	IEEE Xplore Digital Library
Author	Lim, T. Jimenez, J. Benech, P. Fournier, J. Heitz, B. Galy, P.
Copyright Year	2012
Description	Author affiliation: STMicroelectronics, 850 Rue Jean Monnet, 38920 Crolles, France (Lim, T.; Jimenez, J.; Heitz, B.; Galy, P.) \|\| IMEP-LAHC, 3 Parvis Louis Néel, BP 257, 38016 Grenoble Cedex, France (Benech, P.; Fournier, J.)
Abstract	Advanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharges (ESD) issues become more significant. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of the RFICs. ESD protection size dimensions are also an issue to protect RFICs. This paper presents an ESD solution and model able to be implemented in an I/O pad to protect RFICs in advanced CMOS technologies.
Starting Page	175
Ending Page	177
File Size	849599
Page Count	3
File Format	PDF
ISBN	9781467317177
e-ISBN	9781467317177
DOI	10.1109/ISCDG.2012.6360027
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-24
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transmission lines Electrostatic discharges (ESD) Advanced CMOS technology BiCMOS integrated circuits Electrostatic discharges Silicon Discharges (electric) Broadband communication Integrated Radio-frequency integrated circuit (RFIC)
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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