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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Muralikrishna, B. Madhumati, G.L. Khan, H. Deepika, K.G. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of ECE, KL Univ., Vijayawada, India (Khan, H.) || Dept. of ECE, KL Univ., Vaddeswaram, India (Muralikrishna, B.) || Dept. of ECE, Dhanekula Inst. of Eng. & Technol., Vijayawada, India (Madhumati, G.L.) || Dept. of ECE, ALIET, Vijayawada, India (Deepika, K.G.) |
| Abstract | System-on-Chip (SoC) design integrates processors, memory, and a variety of IPs in a single design. Due to the FPGA capabilities and high time-to-market pressures, complex SoC designs are increasingly targeted to FPGA. Traditionally cores in FPGAs are connected using AXI and PLB bus-based architectures. FPGA devices provide Embedded Systems development with new alternatives for creating new hardware accelerated applications. The availability of embedded processor subsystems in FPGAs opens the door to a myriad of applications. Reconfigurable System-on-Chip architecture: includes MicroBlaze Soft Core Processor integrates peripherals with PLB and OPB Buses provides access to memory, PS2 and VGA IP cores. A new peripheral based Arithmetic application is designed, the keyboard module is a custom hardware module that accepts input from a PS/2 serial keyboard and outputs character data to the VGA input memory. VHDL Language is used in ISE for custom logic design. SystemC & VHDL Co-Synthesis scenario provides a way of checking interoperability of a single designed different functionality hardware module. Both designs are synthesizable and implemented in a single Bitstream, and configured to FPGA. Two level functionality is observed for the configured Bitstream with FPGA Hardware, design modeling was done using SystemC & VHDL Co-Synthesis. This paper presents an evaluation of design methods and concepts of reconfigurable architecture; it provides a lot of options for system designers. Co-Synthesis was done either Top-Down or Bottom-Up Design Methodologies. Implementation was targeted through Spartan - 3E FPGA Board. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 772086 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479913565 |
| DOI | 10.1109/ICDCSyst.2014.6926215 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-03-06 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | IP cores Program processors Design methodology Co-Synthesis System-on-Chip Keyboards Hardware MicroBlaze FPGA System-on-chip Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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