NDLI: Parity Preserving Adder/Subtractor Using a Novel Reversible Gate

Content Provider	IEEE Xplore Digital Library
Author	Khandelwal, R. Saini, S.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Commun. Eng., LNM Inst. of Inf. Technol., Jaipur, India (Khandelwal, R.; Saini, S.)
Abstract	Modern VLSI circuit design is governed by low power consumption requirements of ICs. Reversible logic has received great importance because of no information bit loss during computation which results in low power dissipation. Moreover, there is a need to convert the reversible circuits into fault tolerant reversible circuits to detect the occurrence of errors. Parity preserving property can be used for this. A new 5*5 parity preserving reversible gate is proposed in this paper, named as P2RG. The most significant aspect of this work is that it can work both as a full adder and a full subtract or by using one P2RG and Fred kin gate only. Proposed design is better in terms of gate count, garbage outputs, constant inputs and area than the existing similitudes. Thus, this paper provides the initial threshold to design more complex systems which will be able to execute more complicated operations using parity preserving reversible logic.
Sponsorship	IETE Gwalior Sub Center
Starting Page	885
Ending Page	888
File Size	332266
Page Count	4
File Format	PDF
e-ISBN	9781479917976
DOI	10.1109/CSNT.2015.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-04-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computers Fault tolerance P2RG Fault tolerant systems Reversible logic Parity Preserving Logic gates Power dissipation Circuit faults Adders Adder/Subtractor
Content Type	Text
Resource Type	Article

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Index Terms—Reversible Logic Gates, Parity Preserving reversible Logic Gates, Full Adder/Subtractor, Parallel

Design of fault tolearnt full Adder/Subtarctor using reversible gates

Fault tolerant and testable designs of reversible sequential building blocks

Design and synthesis of fault tolerant full adder/subtractor using reversible logic gates.

Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis

Towards the design of fault tolerant reversible circuits components of ALU using new PCMF gate

Novel design of one digit high speed carry select bcd subtractor using reversible logic gates.

Design of Low Logical Cost Conservative Reversible Adders Using Novel PCTG

© 2008 science publications a novel fault tolerant reversible gate for nanotechnology based systems.

Parity Preserving Adder/Subtractor Using a Novel Reversible Gate

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