NDLI: A high speed power efficient pipeline ADC in 0.18μm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Vatanjou, A.A. Dadashi, A. Sobhi, J. Koozehkanani, Z.D.
Copyright Year	2013
Description	Author affiliation: IC Design Res. Lab., Univ. of Tabriz, Tabriz, Iran (Vatanjou, A.A.; Dadashi, A.; Sobhi, J.; Koozehkanani, Z.D.)
Abstract	This paper describes a 12 bit pipeline ADC with conversion rate of 160 MS/s. A 2.5 bit non-flip-around MDAC structure is used in each stage which reduces total number of stages and total amount of sampling capacitance and consequentially power consumption of the ADC. Two-stage indirect compensated opamp with different phase margins in sampling and amplifying modes is embedded in the MDAC and to achieve required accuracy, dc-gain of the opamp is increased using positive feedback in the first stage of the opamp. Simulation results with Spice in 0.18 μm at a temperature of 75°C confirm that with a sampling rate of 160 Ms/s SNDR is 65.6 dB and power consumption is 103 mw where supply voltage is 1.8 V.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1
Ending Page	4
File Size	831741
Page Count	4
File Format	PDF
ISBN	9781467361057
e-ISBN	9781467361040
DOI	10.1109/FTFC.2013.6577749
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline ADC Power demand Pipelines Redundant-Signe-Digit (RSD) Capacitance CMOS integrated circuits Mathematical model Multiplying Digital to Analog Converter (MDAC) Equations Analog-digital conversion
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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