NDLI: HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Corre, Y. Hoang, V.-T. Diguet, J.-P. Heller, D. Lagadec, L.
Copyright Year	2012
Description	Author affiliation: Lab-STICC, Université de Bretagne Occidentale, 29200 Brest, France (Lagadec, L.) \|\| Lab-STICC, Université de Bretagne Sud, 56100 Lorient, France (Corre, Y.; Hoang, V.-T.; Diguet, J.-P.; Heller, D.)
Abstract	Over the last decade many academic and industrial system synthesis and codesign tools have been proposed to designers. However most of these tools are based on IP Libraries but either these libraries are incomplete or are simply not adapted to the targets and constraints. It means that something important is missing when it comes to real implementations. We address this question in this paper and propose a flexible, fast and practical solution. We use high level synthesis (HLS) to obtain fast estimations of hardware accelerators that can then be embedded within the loop of a larger design space exploration flow. Once some solutions are selected they can be directly reuse to synthesise and produce real IPs. In this paper we present the approach and the tool as a key component of our heterogeneous multiprocessor synthesis framework.
Starting Page	1
Ending Page	8
File Size	229839
Page Count	8
File Format	PDF
ISBN	9781467320894
e-ISBN	9782953998726
e-ISBN	9782953998740
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-23
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	ECSI
Subject Keyword	Estimation Accelerator architectures Computer architecture Hardware Libraries Software High level synthesis IP networks System-on-a-chip Field programmable gate arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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