NDLI: SOC HW/SW co-verification technology for application of FPGA test and diagnosis

Content Provider	IEEE Xplore Digital Library
Author	Ruan, A.W. Wang, Y. Shi, K. Zhu, Z.J. Wu, Q. Han, X. Liao, Y.B.
Copyright Year	2011
Description	Author affiliation: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China Chengdu, 610054, China (Ruan, A.W.; Wang, Y.; Shi, K.; Zhu, Z.J.; Wu, Q.; Han, X.; Liao, Y.B.)
Abstract	Process of configuration and fault scan is required to be repeated many times before all resources of a FPGA-under-test are tested and diagnosed. Both FPGA test system and test schemes have been studied and presented in the keynote. Construction of the in-house developed FPGA test system is based on SOC HW/SW co-verification technology. Algorithms for FPGA test and diagnosis covering all FPGA resources such as, configurable logic blocks (CLBs), interconnect resources (IRs), input/output blocks (IOBs), wide edge decoder, et al with minimum configuration numbers are also discussed. Not only multiple faults in FPGA can be detected, but location and type of the multiple faults can also be determined by the FPGA test system and associated test schemes. Furthermore, 100% fault coverage can be achieved in experiment.
Starting Page	1
Ending Page	6
File Size	1157417
Page Count	6
File Format	PDF
ISBN	9781457706028
e-ISBN	9781457706035
e-ISBN	9781457706011
DOI	10.1109/ICCPS.2011.6092258
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Vectors Hardware Software Table lookup Circuit faults Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A HW/SW Co-Verification Technique for Field Programmable Gate Array (FPGA) Test

An evaluation of the application dependent FPGA test method

Interconnect resources testing and faults diagnosis in field programmable gate arrays

Integrated ISS and FPGA SoC HW/SW Co-verification environment design

HW/SW co-design for Esterel processing

Application dependent FPGA testing method using compressed deterministic test vectors

Automatic configuration generation for a SOC co-verification technology based FPGA functional test system

Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign

A bitstream readback based FPGA test and diagnosis system

SOC HW/SW co-verification technology for application of FPGA test and diagnosis

Similar Documents

A HW/SW Co-Verification Technique for Field Programmable Gate Array (FPGA) Test

An evaluation of the application dependent FPGA test method

Interconnect resources testing and faults diagnosis in field programmable gate arrays

Integrated ISS and FPGA SoC HW/SW Co-verification environment design

HW/SW co-design for Esterel processing

Application dependent FPGA testing method using compressed deterministic test vectors

Automatic configuration generation for a SOC co-verification technology based FPGA functional test system

Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign

A bitstream readback based FPGA test and diagnosis system

SOC HW/SW co-verification technology for application of FPGA test and diagnosis