NDLI: Modeling, evaluation and mitigation of SEU error in three-dimensional FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Osgooi, M.N. Jahanian, A. Zarandi, H.R.
Copyright Year	2012
Description	Author affiliation: Dept. of Electrical and Computer Eng., Shahid Beheshti University, G. C., Velenjak, Tehran, Iran (Jahanian, A.) \|\| Dept. of Electrical, IT and Computer Eng., Qazvin Branch, Islamic Azad University, Nokhbegan Blv., Qazvin, Iran (Osgooi, M.N.) \|\| Dept. of Computer Eng. and IT, Amirkabir Univ. of Tech. (Tehran Polytechnic), Hafez St., Tehran, Iran (Zarandi, H.R.)
Abstract	SEU error which is made by various radiations affects the signal integrity of nano-scale circuits, especially for future ultra-large and complex circuits. In this paper, we proposed a SEU error model for three-dimensional FPGAs and evaluate the SEU error of 3D-FPGAs based on the proposed model and then compare the SEU error rate of 3D-FPGAs with 2D-FPGAs. Moreover, we proposed a 3D layer assignment for improving SEU error possibility on three-dimensional FPGAs. The experimental results show that SEU error rate and critical delay decreases about 67% and 13.1% on 4 layers 3D-FPGA compared with 2D-FPGAs, respectively. In addition, the proposed layer assignment improves the possibility of SEU error of 3D-FPGAs up to 6.5% for large FPGA circuits.
Starting Page	31
Ending Page	36
File Size	548547
Page Count	6
File Format	PDF
ISBN	9781467314817
e-ISBN	9781467314824
DOI	10.1109/CADS.2012.6316415
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-02
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Single event upset Switches Neutrons Layer assignment Routing Three dimensional FPGA Circuit faults Field programmable gate arrays Delay
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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