NDLI: A novel technique for tuning low voltage linear transconductor

Content Provider	IEEE Xplore Digital Library
Author	Bhadauria, V. Kant, K.
Copyright Year	2010
Description	Author affiliation: Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology, Allahabad 211004, INDIA (Bhadauria, V.) \|\| Computer Science and Engineering Department, Motilal Nehru National Institute of Technology, Allahabad 211004, INDIA (Kant, K.)
Abstract	In this paper a novel technique is presented to tune a low voltage linear transconductor. Bias offset is used for tunability and bias currents of cross coupled differential amplifiers are adjusted to minimize third harmonic distortion. Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology is used to simulate the proposed circuit. Simulation results show that for the biasing current of 270 µA (Gm of 215 µS), the circuit exhibits less than −30 dB total third harmonic distortion (HD3) at 1 Vp-p @ 50 MHz and at low voltage supply.
Starting Page	22
Ending Page	25
File Size	465199
Page Count	4
File Format	PDF
ISBN	9781424466290
e-ISBN	9781424466320
DOI	10.1109/ICEDSA.2010.5503108
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-11
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Analog CMOS Circuit MOS Transconductors Linearization Techniques CMOS process MOSFETs Harmonic Distortion Analysis Low voltage Coupling circuits Transconductors CMOS technology Operational Transconductance Amplifier (OTA) Differential amplifiers Harmonic distortion Transconductance
Content Type	Text
Resource Type	Article

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