NDLI: A new high-resolution and high-speed open-loop CMOS sample and hold circuit

Content Provider	IEEE Xplore Digital Library
Author	Abolhasani, A. Hadidi, K. Tohidi, M. Khoei, A.
Copyright Year	2013
Description	Author affiliation: Microelectron. Res. Lab., Univ. of Urmia, Urmia, Iran (Abolhasani, A.; Hadidi, K.; Tohidi, M.; Khoei, A.)
Abstract	A new open loop, high resolution CMOS sample and hold (S/H) circuit is presented in this article. This structure is designed based on a new method in order to decrease dependency of the storing charge of holding capacitors to the charge injection of transistors. It is constructed of dummy switches and auxiliary capacitor to decrease the voltage spikes that are produced during the sampling mode. Due to the high linearity feature of our proposed design in comparison with previous works, it has been reached to a great improvement in signal to noise ratio (SNR) up to about 15dB. Also, its ENOB have been increased to 16 bits. Another advantages of our proposed design are its lower power dissipation and its high input voltage range. Also the optimum functionality of our proposed circuit does not damaged by the process variations in different corners. As our proposed S/H circuit has been designed in open loop structure, it is suitable for high speed applications.
Starting Page	1
Ending Page	6
File Size	1228141
Page Count	6
File Format	PDF
ISBN	9781467356343
DOI	10.1109/IranianCEE.2013.6599858
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-14
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sample and hold circuit High linear High speed sampling Capacitors Linearity Logic gates Analog to digital converter Threshold voltage CMOS integrated circuits Transistors Clocks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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