NDLI: Modeling of layout-dependent stress effect in CMOS design

Content Provider	IEEE Xplore Digital Library
Author	Chi-Chao Wang Wei Zhao Liu, F. Min Chen Yu Cao
Copyright Year	2009
Description	Author affiliation: Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA (Chi-Chao Wang; Wei Zhao; Min Chen; Yu Cao) \|\| IBM Austin Res. Lab., Austin, TX, USA (Liu, F.)
Abstract	Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90 nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45 nm node.
Starting Page	513
Ending Page	520
File Size	880104
Page Count	8
File Format	PDF
ISBN	9781605588001
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Semiconductor device modeling Stress Capacitive sensors Circuit simulation CMOS technology Integrated circuit technology Fabrication Threshold voltage Bridge circuits Design optimization Mobility Layout Dependence Stress Effect Pattern Decomposition Stress Modeling
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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