NDLI: Cost analysis of chip scale packaging

Content Provider	IEEE Xplore Digital Library
Author	Lo-Soun Su Louis, M. Reber, C.
Copyright Year	1997
Description	Author affiliation: IBM (SEMATECH), Austin, TX, USA (Lo-Soun Su)
Abstract	This paper documents a chip scale package (CSP) cost analysis using SEMATECH's Cost/Resource Model (CRM). The intent of the analysis was to compare costs between CSPs and conventional package technologies such as the thin small outline package (TSOP) and ball grid array (BGA) to determine whether CSP is a viable packaging technology. The analysis includes costs of both package and board assembly components in a high volume, mature production factory. Four representative CSP types (custom lead frame, flex circuit interposer, rigid substrate interposer, and wafer level assembly) and three traditional surface mount package configurations (plastic ball grid array [PBGA], ceramic ball grid array [CBGA], and thin small outline package [TSOP]) were selected to benchmark. By selecting CSPs across many applications and I/O ranges, the goal was to study a cross section of CSPs that were in or near production. Analysis results indicated that CSPs with a low I/O count are cost-competitive with conventional surface mount packages and can be used with the existing printed circuit board (PCB) infrastructure. However, CSPs with a high I/O count are not currently supported by conventional PCB technology and are not cost-competitive with conventional surface mount package technology.
Starting Page	216
Ending Page	223
File Size	1073672
Page Count	8
File Format	PDF
ISBN	0780339290
ISSN	10898190
DOI	10.1109/IEMT.1997.626921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Chip scale packaging Wafer scale integration Electronics packaging Assembly Plastic packaging Surface-mount technology Production facilities Flexible electronics Lead
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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