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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hang-Ting Lue Pei-Ying Du Tzu-Hsuan Hsu Yi-Hsuan Hsiao Sheng-Chih Lai Szu-Yu Wang Shih-Ping Hong Ming-Tsung Wu Hsu, F.H. Lien, N.Z. Chi-Pin Lu Jung-Yu Hsieh Ling-Wu Yang Tahone Yang Kuang-Chao Chen Kuang-Yeu Hsieh Liu, R. Chih-Yuan Lu |
| Copyright Year | 2009 |
| Description | Author affiliation: Technology Development Center, 16, Li-Hsin Road, Hsinchu Science Park, Taiwan (Szu-Yu Wang; Shih-Ping Hong; Ming-Tsung Wu; Hsu, F.H.; Lien, N.Z.; Chi-Pin Lu; Jung-Yu Hsieh; Ling-Wu Yang; Tahone Yang; Kuang-Chao Chen) || Macronix International Co. Ltd, Emerging Central Lab., 16, Li-Hsin Road, Hsinchu Science Park, Taiwan (Hang-Ting Lue; Pei-Ying Du; Tzu-Hsuan Hsu; Yi-Hsuan Hsiao; Sheng-Chih Lai; Kuang-Yeu Hsieh; Liu, R.; Chih-Yuan Lu) |
| Abstract | Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits of CT and FG - CT for good retention and scaling to few-electron regime and FG for edge effect immunity and faster erase. The planar “fusion” FG/CT devices are fabricated by replacing the conventional IPD ONO of a FG device by a CT BE-SONOS structure. Both simulation and experimental results indicate that most of the stored electrons are trapped inside the SiN trapping layer instead of the FG. The CT storage provides excellent retention even for a very thin tunnel oxide (≪5nm). On the other hand, the thin FG provides an equipotential channel that screens any non-uniform injection effect. Excellent memory window, scalability and reliability are demonstrated. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1265389 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424456390 |
| e-ISBN | 9781424456413 |
| e-ISBN | 9781424456406 |
| DOI | 10.1109/IEDM.2009.5424214 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Dielectric devices High K dielectric materials High-K gate dielectrics Tunneling Nonvolatile memory Electron traps Voltage Electronic mail Silicon compounds Scalability |
| Content Type | Text |
| Resource Type | Article |
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