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Content Provider | IEEE Xplore Digital Library |
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Author | Araneda, L. Figueroa, M. |
Copyright Year | 2014 |
Description | Author affiliation: Dept. of Electr. Eng., Univ. of Concepcion, Concepcion, Chile (Araneda, L.; Figueroa, M.) |
Abstract | We present a hardware architecture for real-time digital video stabilization in high-performance embedded systems. The stabilization algorithm analyzes the current and past video frames and obtains a motion estimation vector, which is then filtered to isolate unwanted camera movements from intentional panning. The vector is then used to correct the output video frame. We designed a hardware architecture for motion estimation, filtering and correction and implemented it on a Xilinx Spartan-6 LX45 Field Programmable Gate Array (FPGA). Running on the 640x480-pixel video output of an infrared camera, the circuit successfully compensates involuntary camera motion at a maximum throughput of 104.15 frames per second and dissipates 24.16mW of power with a 100MHz clock. |
Starting Page | 90 |
Ending Page | 97 |
File Size | 542864 |
Page Count | 8 |
File Format | |
ISBN | 9781479957934 |
DOI | 10.1109/DSD.2014.26 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2014-08-27 |
Publisher Place | Italy |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Vectors Cameras Motion estimation Hardware Streaming media Measurement Jitter FPGA digital image stabilization embedded systems video processing |
Content Type | Text |
Resource Type | Article |
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