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Content Provider | IEEE Xplore Digital Library |
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Author | Celedon, N. Redlich, R. Figueroa, M. |
Copyright Year | 2012 |
Abstract | Despite recent technological advances which improve their performance and reduce their cost, Focal Plane Arrays for infrared imagers suffer from spatial nonuniformity that renders their output unusable unless a suitable correction method is applied. This paper describes an embedded hardware implementation of Scribner's algorithm for online nonuniformity correction. Our implementation on a Xilinx Spartan XC3S1200E FPGA achieves a throughput of more than 130 frames per second on 320x240-pixel IR video, which greatly exceeds real-time requirements. The power consumption of our system is 329mW, which is two orders of magnitude smaller than a software implementation of the algorithm on a traditional processor, and can be greatly reduced with a custom-VLSI implementation of the architecture. |
Starting Page | 193 |
Ending Page | 200 |
File Size | 745720 |
Page Count | 8 |
File Format | |
ISBN | 9781467324984 |
e-ISBN | 9780769547985 |
DOI | 10.1109/DSD.2012.64 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2012-09-05 |
Publisher Place | Turkey |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Streaming media Cameras Field programmable gate arrays Random access memory Noise Hardware Neural networks Field-programmable gate array Nonuniformity correction Neural network Smart IR camera |
Content Type | Text |
Resource Type | Article |
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