NDLI: Experimental SEU Impact on Digital Design Implemented in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Kvasnicka, J. Kubalik, P. Kubatova, H.
Copyright Year	2008
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Czech Tech. Univ. in Prague, Prague (Kvasnicka, J.; Kubalik, P.; Kubatova, H.)
Abstract	The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is performed in the user-selected area. Look-up-tables, cell interconnections, cell-to-bus connections and routing resources are considered. Other FPGA resources are not considered. Combinatorial circuits and MCNC benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture.
Starting Page	100
Ending Page	103
File Size	253694
Page Count	4
File Format	PDF
ISBN	9780769532776
DOI	10.1109/DSD.2008.119
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-03
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Circuit faults Single event upset Circuit testing Random access memory Electrical fault detection Fault detection Programmable logic arrays Table lookup Integrated circuit interconnections dependability computation SEU emulator on-line testing FPGA
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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