NDLI: Carrier-Based Approach: A Generous Strategy to Develop Compact Model of Non-Classical CMOS

Content Provider	IEEE Xplore Digital Library
Author	Jin He Xing Zhang Chan, M. Yangyuan Wang
Copyright Year	2006
Description	Author affiliation: Inst. of Micro-Electron., Peking Univ., Beijing (Jin He; Xing Zhang)
Abstract	As traditional CMOS is gradually approaching the limit of the bulk technology scaling, non-classical CMOS devices such as UTB-SOI, DG-MOSFET and MG structure provide a path to scale CMOS to the end of the Roadmap using new transistor structural designs. Compact modeling of such non-classical MOSFET devices calls for a fundamentally different approach from the conventional bulk CMOS because of the different device physics picture and unique physical effects in the new topology of the non-classical CMOS devices. This paper outlines the carrier-based approach: A generous strategy to develop the compact model of non-classical MOSFETs. It is shown that the carrier-based analytic models of UTB-SOI, DG and SRG MOSFETs can be developed in terms of the induced carrier concentration rather than the traditional surface potential or the charge variable. Based on an exact solution of the Poisson equation in various non-classical structures coupled to the Pao-Sah current formulation in terms of the carrier concentration, the different dependences of the surface potential, centric potential, inversion charge and the current on the silicon body thickness and the gate oxide are elucidated analytically and then the predicted IV characteristics are compared with the 2-D and 3-D numerical simulations. The analytical results of the model presented show in a good agreement with the numerical simulation, demonstrating the model is valid for all operation regions and traces the transition between them without any auxiliary variable and function
Starting Page	167
Ending Page	172
File Size	7365226
Page Count	6
File Format	PDF
ISBN	1424400414
DOI	10.1109/ICCDCS.2006.250855
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-26
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling CMOS technology Physics Numerical simulation Silicon on insulator technology MOSFETs Topology Poisson equations Switches Circuits and systems Compact modeling Non-classical CMOS Device physics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A carrier-based analytic model for undoped (lightly doped) ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs

A Complete Carrier-Based Non-Charge-Sheet Analytic Model for Nano-Scale Undoped Symmetric Double-Gate MOSFETs

A Unified Carrier-Based Model for Symmetric Double-Gate and Surrounding-Gate MOS Transistors

ULTRA-SOI: New generation of SOI CMOS model with physics based dynamic depletion characteristics

New Explicit Charge and Capacitance Models for Undoped Surrounding Gate MOSFETs

A Complete Surface Potential-Based Core Model for the Undoped Symmetric Double-Gate MOSFETs

Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges

Non-classical CMOS device design

A study of CMOS radiation tolerant transistors using green functions

Carrier-Based Approach: A Generous Strategy to Develop Compact Model of Non-Classical CMOS

Similar Documents

A carrier-based analytic model for undoped (lightly doped) ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs

A Complete Carrier-Based Non-Charge-Sheet Analytic Model for Nano-Scale Undoped Symmetric Double-Gate MOSFETs

A Unified Carrier-Based Model for Symmetric Double-Gate and Surrounding-Gate MOS Transistors

ULTRA-SOI: New generation of SOI CMOS model with physics based dynamic depletion characteristics

New Explicit Charge and Capacitance Models for Undoped Surrounding Gate MOSFETs

A Complete Surface Potential-Based Core Model for the Undoped Symmetric Double-Gate MOSFETs

Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges

Non-classical CMOS device design

A study of CMOS radiation tolerant transistors using green functions

Carrier-Based Approach: A Generous Strategy to Develop Compact Model of Non-Classical CMOS