NDLI: Synthesis for mixed CMOS/PTL logic

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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

Proceedings Design, Automation and Test in Europe

Synthesis for mixed CMOS/PTL logic

Content Provider	IEEE Xplore Digital Library
Author	Congguang Yang Ciesielski, M.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA (Congguang Yang)
Abstract	Summary form only given. High noise immunity and level-restoring capabilities of static CMOS gates, combined with small area and low power of PTL cells, make a mixed CMOS/PTL design style an ideal alternative to the all-CMOS technology. However, the synthesis of mixed CMOS/PTL circuits imposes a great challenge to the existing synthesis methodology. Neither traditional techniques based on algebraic factorization nor methods based on direct BDD mapping are applicable to this new circuit style. We have recently proposed a new BDD-based logic optimization method for static CMOS. It is based on iterative BDD decomposition using various dominators which correspond to decomposable BDD structures leading to AND, OR, XOR and MUX decompositions. Synthesis results show that the method is very efficient for both AND/OR- and XOR-intensive functions. Since PTL structures can be easily identified on a BDD, our method can be readily extended to perform logic decomposition leading to mixed CMOS/PTL logic implementation. In contrast to other PTL synthesis techniques, based on direct BDD mapping, our method is not limited to decomposition onto PLTs only; its logic decomposition and optimization is driven by the capabilities of both the static CMOS and PTL logic. Our BDD decomposition method can also account for various parameters associated with circuit performance, thus avoiding drawbacks of direct BDD mapping-based synthesis, such as large fanouts and long transistor chains.
File Size	38439
File Format	PDF
ISBN	0769505376
DOI	10.1109/DATE.2000.840883
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-03-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS logic circuits Binary decision diagrams Circuit synthesis Optimization methods Circuit noise Noise level CMOS technology Data structures Boolean functions Circuit optimization
Content Type	Text
Resource Type	Article

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