NDLI: Principles of the SYCO Compiler

Content Provider	IEEE Xplore Digital Library
Author	Jerraya, A. Varinot, P. Jamier, R. Courtois, B.
Copyright Year	1986
Description	Author affiliation: IMAG/TIM3, GRENOBLE, FRANCE (Jerraya, A.)
Abstract	The SYCO system is a silicon compiler for VLSI circuits specified by algorithms. The SYCO system starts from an algorithmic description and produces a microprocessor-like circuit that realizes the algorithm. It uses a target architecture based on a multiple interpretation level scheme. A large interpreter of a given command language is split into a set of interpreter levels. Each interpreter level breaks down the commands given by the upper level into a set of sub-commands for the lower level. Each interpreter level is implemented by a block of layout called a layout slice. A chip will contain one data path slice and several control section slices. The SYCO system makes use of a set of specialized compilers to produce the layout of the datapath and of the control section slices. These slices are generated to be automatically assembled together. The whole system is written in Le Lisp. It is expected that the SYCO system will give the ability to compile circuits, which have the complexity of the MC68000. The SYCO system is developped in the framework of the SYCOMORE French National Project for CAD of VLSI.
Starting Page	715
Ending Page	721
File Size	1103590
Page Count	7
File Format	PDF
ISBN	0818607025
ISSN	0738100X
DOI	10.1109/DAC.1986.1586169
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-06-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon compiler Automatic control Integrated circuit synthesis Very large scale integration Control systems Assembly Command languages Integrated circuit layout Software tools Circuit synthesis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Methods for Hierarchical Automatic Layout of Custom LSI Circuit Masks

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