NDLI: FastRoute 2.0: A High-quality and Efficient Global Router

Content Provider	IEEE Xplore Digital Library
Author	Min Pan Chu, C.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA (Min Pan; Chu, C.)
Abstract	Because of the increasing dominance of interconnect issues in advanced IC technology, it is desirable to incorporate global routing into early design stages to get accurate interconnect information. Hence, high-quality and fast global routers are in great demand. In this paper, we propose two major techniques to improve the extremely fast global router, FastRoute (Pan and Chu, 2006) in terms of solution quality : (1) monotonic routing, (2) multi-source multi-sink maze routing. The new router is called FastRoute 2.0. Experimental results show that FastRoute 2.0 can generate high-quality routing solutions with fast runtime compared with three state-of-the-art academic global routers FastRoute, Labyrinth (Kastner et al., 2000) and Chi Dispersion router (Hadsell and Madden, 2003). On the set of benchmarks used in Pan and Chu, 2006 and Hadsell and Madden (2003), the total overflow of FastRoute 2.0 is 98, compared to 1012 (FastRoute), 2846 (Labyrinth) and 1271 (Chi Dispersion Router). The runtime of FastRoute 2.0 is 73% slower than FastRoute, but 78times and 37times faster than Labyrinth and Chi Dispersion router. The promising results make it possible to integrate global routing into early design stages. This could dramatically improve the design solution quality.
Starting Page	250
Ending Page	255
File Size	264533
Page Count	6
File Format	PDF
ISBN	1424406293
DOI	10.1109/ASPDAC.2007.357994
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-23
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Integrated circuit interconnections Runtime Timing Delay estimation White spaces Topology Very large scale integration Clocks Wire
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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