NDLI: A technology-independent methodology of placement generation for analog circuit

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A technology-independent methodology of placement generation for analog circuit

Content Provider	IEEE Xplore Digital Library
Author	Wai-Chee Wong Chan, P.C.H. Wai-On Law
Copyright Year	1999
Description	Author affiliation: Hong Kong Univ. of Sci. & Technol., Hong Kong (Wai-Chee Wong)
Abstract	An automatic placement system with emphasis on technology independent methodology and device matching consideration for analog layout design is presented. A novel optimization approach based on circuit partitioning, simulated annealing and a branch-and-bound algorithm is proposed to solve the placement problem. The move set used to generate perturbations for annealing is capable of arriving at any topological placement. The branch-and-bound is modified to take circuit performance into consideration. Results of two silicon proven designs generated by the system demonstrate an 8X cycle time reduction as compared to a manual approach.
Starting Page	141
Ending Page	144
File Size	507944
Page Count	4
File Format	PDF
ISBN	078035012X
DOI	10.1109/ASPDAC.1999.759980
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-01-21
Publisher Place	Hong Kong
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analog circuits Circuit simulation Simulated annealing Circuit optimization Routing Degradation Partitioning algorithms Silicon Costs Integer linear programming
Content Type	Text
Resource Type	Article

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