NDLI: Transistor reordering rules for power reduction in CMOS gates

Content Provider	IEEE Xplore Digital Library
Author	Wen-Zen Shen Jiing-Yuan Lin Fong-Wen Wang
Copyright Year	1995
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Wen-Zen Shen)
Abstract	The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power consumption. In this paper, based on the input signal probabilities and transition densities, we propose a set of simple transistor reordering rules for both basic and complex CMOS gates to minimize the transition counts at the internal nodes. The most attractive feature of this approach is that not only the power consumption is reduced efficiently, but also the other performances are not degraded. Experimental results show that this technique typically reduces the power by about 10% in average, but in some cases the improvement is even 35%.
Starting Page	1
Ending Page	6
File Size	666355
Page Count	6
File Format	PDF
ISBN	4930813670
DOI	10.1109/ASPDAC.1995.486193
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-08-29
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption CMOS logic circuits Power dissipation Logic gates Voltage Capacitance Degradation Very large scale integration Integrated circuit technology Signal processing
Content Type	Text
Resource Type	Article

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Transistor reordering rules for power reduction in CMOS gates