NDLI: Error-free computation of 8/spl times/8 2D DCT and IDCT using two-dimensional algebraic integer quantization

Content Provider	IEEE Xplore Digital Library
Author	Wahid, K. Dimitrov, V. Jullien, G.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada (Wahid, K.; Dimitrov, V.; Jullien, G.)
Abstract	This paper presents a novel error-free (infinite-precision) architecture for the fast implementation of both 8/spl times/8 2D discrete cosine transform and inverse DCT. The architecture uses a new algebraic integer quantization of a 1D radix-8 DCT that allows the separable computation of a 2D 8/spl times/8 DCT without any intermediate number representation conversions. This is a considerable improvement on previously introduced algebraic integer encoding techniques to compute both DCT and IDCT which eliminates the requirements to approximate the transformation matrix elements by obtaining their exact representations and hence mapping the transcendental functions without any errors. Using this encoding scheme, an entire 8/spl times/8 1D DCT-SQ (scalar quantization) algorithm can be implemented with only 24 adders. Apart from the multiplication-free nature, this new mapping scheme fits to this algorithm, eliminating any computational or quantization errors and resulting short-word-length and high-speed-design.
Starting Page	214
Ending Page	221
File Size	165007
Page Count	8
File Format	PDF
ISBN	0769523668
ISSN	10636889
DOI	10.1109/ARITH.2005.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Two dimensional displays Discrete cosine transforms Quantization Image coding Computer architecture Polynomials Computer errors Hardware Laboratories Discrete transforms
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A cost-effective architecture for 8/spl times/8 two-dimensional DCT/IDCT using direct method

VLSI Implementation of fully pipelined multiplierless 2D DCT/IDCT architecture for JPEG

Fast 8/spl times/8 DCT pruning algorithm

A Row-Parallel 8$,times,$ 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT

Parallel-pipeline 8/spl times/8 forward 2-D ICT processor chip for image coding

A new design and implementation of 8/spl times/8 2-D DCT/IDCT

Fixed-point error analysis and wordlength optimization of a distributed arithmetic based 8/spl times/8 2D-IDCT architecture

Finite wordlength effects analysis and wordlength optimization of a multiplier-adder based 8/spl times/8 2D-IDCT architecture

Error-free computation of 8/spl times/8 2D DCT and IDCT using two-dimensional algebraic integer quantization

Similar Documents

A cost-effective architecture for 8/spl times/8 two-dimensional DCT/IDCT using direct method

VLSI Implementation of fully pipelined multiplierless 2D DCT/IDCT architecture for JPEG

Fast 8/spl times/8 DCT pruning algorithm

A Row-Parallel 8$,times,$ 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT

Parallel-pipeline 8/spl times/8 forward 2-D ICT processor chip for image coding

A new design and implementation of 8/spl times/8 2-D DCT/IDCT

Fixed-point error analysis and wordlength optimization of a distributed arithmetic based 8/spl times/8 2D-IDCT architecture

Finite wordlength effects analysis and wordlength optimization of a multiplier-adder based 8/spl times/8 2D-IDCT architecture

Error-free computation of 8/spl times/8 2D DCT and IDCT using two-dimensional algebraic integer quantization