NDLI: Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification

Content Provider	IEEE Xplore Digital Library
Author	Selvaraj, H. Sapiecha, P. Dhavlikar, N.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Nevada Univ., Las Vegas, NV, USA (Selvaraj, H.)
Abstract	The ASIC designs are growing larger everyday. It is very hard to simulate these designs because the simulation time has risen tremendously. An alternate solution is to partition the large design into modules and perform incremental simulation. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of large ASICs. On the other hand, since the introduction of FPGAs, they have been playing an important role in ASIC design cycle. But due to very large size of today's ASIC designs (millions of gates) compared to FPGAs, it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. This paper takes a large RTL design of an ASIC into consideration, analyzes the size of each module in terms of number of CLBs, I/Os, flip-flops, latches and applies the algorithm to partition it automatically into minimum number of FPGAs.
Starting Page	411
Ending Page	415
File Size	39013
Page Count	5
File Format	PDF
ISBN	0769513123
DOI	10.1109/ICCIMA.2001.970504
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-30
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Application specific integrated circuits Prototypes Field programmable gate arrays Emulation Algorithm design and analysis Circuit simulation Flip-flops Latches Partitioning algorithms
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Using multi-FPGA systems for ASIC prototyping

Emulation: prototyping without the hassles of FPGA-to-ASIC conversion

Integrating HDL synthesis and partitioning for multi-FPGA designs

A mixed design flow for FPGA prototyping of design with scan circuits

ASIC Design and Verification in an FPGA Environment

A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration

50,000 gate ASIC prototyping PLD using four flex 8000 devices and a programmable interconnect

Multi-way Fpga Partitioning By Fully Exploiting Design Hierarchy

Multiple Scenario Approach for Pre-Silicon Hardware/Software Co-Verification

Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification

Similar Documents

Using multi-FPGA systems for ASIC prototyping

Emulation: prototyping without the hassles of FPGA-to-ASIC conversion

Integrating HDL synthesis and partitioning for multi-FPGA designs

A mixed design flow for FPGA prototyping of design with scan circuits

ASIC Design and Verification in an FPGA Environment

A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration

50,000 gate ASIC prototyping PLD using four flex 8000 devices and a programmable interconnect

Multi-way Fpga Partitioning By Fully Exploiting Design Hierarchy

Multiple Scenario Approach for Pre-Silicon Hardware/Software Co-Verification

Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification