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Content Provider | IEEE Xplore Digital Library |
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Author | Tse-Wei Chen Shao-Yi Chien |
Copyright Year | 2009 |
Description | Author affiliation: Media IC and System Lab, Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, BL-421, No. 1, Sec. 4, Roosevelt Rd., Taipei 106, Taiwan (Tse-Wei Chen; Shao-Yi Chien) |
Abstract | K-Means is a clustering algorithm that is widely applied in many fields, including pattern classification and multimedia analysis. Due to real-time requirements and computational-cost constraints in embedded systems, it is necessary to accelerate K-Means algorithm by hardware implementations in SoC environments, where the bandwidth of the system bus is strictly limited. In this paper, a bandwidth adaptive hardware architecture of K-Means clustering is proposed. Experiments show that the proposed hardware has the maximum clock speed 400MHz with TSMC 90nm technology, and it can deal with feature vectors with different dimensions using five parallel modes to utilize the input bandwidth efficiently. |
Starting Page | 573 |
Ending Page | 576 |
File Size | 178095 |
Page Count | 4 |
File Format | |
ISBN | 9781424423538 |
ISSN | 15206149 |
DOI | 10.1109/ICASSP.2009.4959648 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2009-04-19 |
Publisher Place | Taiwan |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Bandwidth Hardware Computer architecture Clustering algorithms Computational intelligence Pattern classification Pattern analysis Algorithm design and analysis Real time systems Embedded computing hardware design K-Means clustering methods pattern recognition parallel architectures |
Content Type | Text |
Resource Type | Article |
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