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Content Provider | IEEE Xplore Digital Library |
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Author | Normile, J. Wright, D. |
Copyright Year | 1991 |
Description | Author affiliation: Apple Computer ATG, Cupertino, CA, USA (Normile, J.; Wright, D.) |
Abstract | The architecture and application of a multiprocessor system based on a homogeneous array of DSP processors are discussed. The system consists of floating point digital signal processors connected to each other via fast serial links. Each processor has access to a globally shared memory, and a multiple bus architecture in combination with a dual ported memory allows communication with a host controller. The architecture has been implemented and applied to the prototyping of video compression algorithms. The algorithms implemented include JPEG still-frame compression, CCITT H.261, and MPEG coding. These techniques may be decomposed into variable length encode or decode portions in tandem with a compute intensive element. This decomposition and its mapping into parallel processors is described.< |
Starting Page | 1121 |
Ending Page | 1124 |
File Size | 433926 |
Page Count | 4 |
File Format | |
ISBN | 0780300033 |
ISSN | 15206149 |
DOI | 10.1109/ICASSP.1991.150563 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1991-04-14 |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Image coding Parallel processing Signal processing algorithms Transform coding Multiprocessing systems Digital signal processing Digital signal processors Communication system control Computer architecture Prototypes |
Content Type | Text |
Resource Type | Article |
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