NDLI: Low power FIR filter FPGA implementation based on distributed arithmetic and residue number system

Content Provider	IEEE Xplore Digital Library
Author	Wei Wang Swamy, M.N.S. Ahmad, M.O.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada (Wei Wang)
Abstract	In this paper, several low power techniques are proposed for the FPGA implementation of a distributed arithmetic and residue number system-based FIR filter. Two algorithms are proposed to reduce the size of the residue-to-binary converter, which is the crucial part of the system. The area, speed and power consumption of the filter is improved accordingly. Furthermore, a lookup table (LUT) partition technique is presented such that the most frequently accessed locations are stored in a smaller memory. The power consumption of the LUTs is reduced because accesses to smaller LUTs dissipate less power. The implementation results show a 20% power reduction by using the proposed methods.
Sponsorship	IEEE Circuits and Syst. Soc.
Starting Page	102
Ending Page	105
File Size	354450
Page Count	4
File Format	PDF
ISBN	078037150X
DOI	10.1109/MWSCAS.2001.986125
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-08-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Field programmable gate arrays Table lookup Energy consumption Digital signal processing Signal processing algorithms Dynamic range Partitioning algorithms Digital arithmetic Application specific integrated circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Distributed Arithmetic for FIR Filter Design on FPGA

Hardware implementation of FIR filter

Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic

FPGA Implementation of an Optimized Coefficients Pulse Shaping FIR Filters

The implementation methods of high speed FIR filter on FPGA

Distributed Arithmetic for FIR Filter implementation on FPGA

RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic

FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters

Implementation of distributed FIR digital filter on FPGA

Low power FIR filter FPGA implementation based on distributed arithmetic and residue number system

Similar Documents

Distributed Arithmetic for FIR Filter Design on FPGA

Hardware implementation of FIR filter

Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic

FPGA Implementation of an Optimized Coefficients Pulse Shaping FIR Filters

The implementation methods of high speed FIR filter on FPGA

Distributed Arithmetic for FIR Filter implementation on FPGA

RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic

FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters

Implementation of distributed FIR digital filter on FPGA

Low power FIR filter FPGA implementation based on distributed arithmetic and residue number system