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Content Provider | IEEE Xplore Digital Library |
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Author | Fang-Ting Chou Zong-Yi Chen Hsing-Chien Chu Chung-Chih Hung |
Copyright Year | 2015 |
Description | Author affiliation: Dept. of Electr. & Comput. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Fang-Ting Chou; Zong-Yi Chen; Hsing-Chien Chu; Chung-Chih Hung) |
Abstract | This paper proposes a new architecture of 12-bit current-steering digital-to-analog converter (DAC) with novel biasing scheme. In the proposed DAC, two 6-bit binary-weighted current source arrays are designed with two reference currents. The technique allows significant area savings without impairing static accuracy. The paper also presents a method to generate dual reference currents, whose design is compact and consumes low static power. The active area of the 12-bit DAC is $0.36mm^{2}$ approximately. This chip was fabricated by a standard 0.18μm CMOS technology, and consumes 38mW at 180MS/s update rate with 1.8V supply voltage. |
Starting Page | 1022 |
Ending Page | 1025 |
File Size | 583395 |
Page Count | 4 |
File Format | |
ISBN | 9781479983919 |
DOI | 10.1109/ISCAS.2015.7168810 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2015-05-24 |
Publisher Place | Portugal |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Transistors Resistors CMOS integrated circuits Layout Impedance Semiconductor device measurement Calibration reference current digital-to-analog converter |
Content Type | Text |
Resource Type | Article |
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