NDLI: VHDL-AMS Statistical Analysis for marginal probabilities

Content Provider	IEEE Xplore Digital Library
Author	Haase, J. Sohrmann, C.
Copyright Year	2009
Description	Author affiliation: Branch Lab Design Automation (EAS), Fraunhofer-Institut Integrierte Schaltungen, Dresden, Germany (Haase, J.; Sohrmann, C.)
Abstract	The impact of parameter variations on components' and systems' characteristics, especially in the area of IC design, has been discussed for several years. To investigate the influence of parameter variations on system characteristics, standard Monte Carlo simulation is often used when exact results cannot be obtained using a deterministic algorithm. However, this procedure may require a huge number of simulation runs if marginal probabilities are estimated. This paper shows how importance sampling as a variance reduction technique can be used for estimating small probabilities in simulation experiments based on the SAE J 2748 VHDL-AMS Statistical Analysis Package. Furthermore, application examples are presented to show how the use of parameter sensitivities can help creating random variable distributions for importance sampling.
Starting Page	114
Ending Page	119
File Size	516841
Page Count	6
File Format	PDF
ISBN	9781424453580
DOI	10.1109/BMAS.2009.5338879
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Statistical analysis Probability Monte Carlo methods Random variables Design automation Analytical models Equations Computational modeling Integrated circuit packaging Yield estimation yield analysis Monte Carlo simulation importance sampling VHDL VHDL-AMS
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation

Robust importance sampling for efficient SRAM yield analysis

Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space

A novel approach to statistical simulation of ICS affected by non-linear variabilities

Monte Carlo Simulation Using VHDL-AMS

In-vehicle communication network statistical analysis using VHDL-AMS behavioral models

Early, accurate and fast yield estimation through Monte Carlo-alternative probabilistic behavioral analog system simulations

An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators

VHDL-AMS Statistical Analysis for Marginal Probabilities Usage of SAE J 2748 Statistical Analysis Package for Importance Sampling

VHDL-AMS Statistical Analysis for marginal probabilities

Similar Documents

Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation

Robust importance sampling for efficient SRAM yield analysis

Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space

A novel approach to statistical simulation of ICS affected by non-linear variabilities

Monte Carlo Simulation Using VHDL-AMS

In-vehicle communication network statistical analysis using VHDL-AMS behavioral models

Early, accurate and fast yield estimation through Monte Carlo-alternative probabilistic behavioral analog system simulations

An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators

VHDL-AMS Statistical Analysis for Marginal Probabilities Usage of SAE J 2748 Statistical Analysis Package for Importance Sampling

VHDL-AMS Statistical Analysis for marginal probabilities