NDLI: Behavioral modeling and simulation of jitter and phase noise in fractional-N PLL frequency synthesizer

Content Provider	IEEE Xplore Digital Library
Author	Xiaojian Mao Huazhong Yang Hui Wang
Copyright Year	2004
Description	Author affiliation: Tsinghua Univ., Beijing, China (Xiaojian Mao; Huazhong Yang; Hui Wang)
Abstract	A methodology is presented for predicting the phase noise and jitter of a fractional-N PLL based frequency synthesizer. Based on the phase/jitter properties extracted from transistor level through simulation, a voltage-domain behavioral model can give phase noise performance of fractional-N PLL frequency synthesizers in system level accurately, while the simulation efficiency is also improved by merging the VCO block operated at the highest frequency into those operated at lower frequency. Comparing to phase-domain simulation, the improved voltage-domain models do a better job of capturing the details of the behavior of the loop, details such as the signal capturing and escaping traces in fractional-N frequency synthesizer.
Sponsorship	IEEE Circuits and Syst. Soc
Starting Page	25
Ending Page	30
File Size	324751
Page Count	6
File Format	PDF
ISBN	0780386159
DOI	10.1109/BMAS.2004.1393977
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Jitter Phase noise Phase locked loops Frequency synthesizers Predictive models Circuit simulation Voltage Delta-sigma modulation 1f noise Partial response channels
Content Type	Text
Resource Type	Article

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