NDLI: Research on generating the constants T[i] of MD5 algorithm based on FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Liu Yuan-feng Dai Zi-bin Xu Jian
Copyright Year	2005
Description	Author affiliation: Inst. of Electron. Technol., Inf. Eng. Univ., Zhengzhou (Liu Yuan-feng; Dai Zi-bin; Xu Jian)
Abstract	This paper critically analyze the character of the constant T[i] of MD5 hash algorithm. Unlike previous works which rely on look-up tables to store constant T[i], the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, which is efficient and secure, suitable for FPGAs implementation. The new design introduces the feedback shift register and the nonlinear feedback shift register to generate the constant T[i] instead of storing directly based on FPGAs. To compare with traditional schemes, experiment results show that the required logic elements reduce 84% and the output's delay reduces 38%. Finally, this paper presents a good research trend for resolving the storage in hardware implementation using FPGAs
Starting Page	733
Ending Page	736
File Size	468620
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611434
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Shift registers Hardware Delay Data security Switches Linear feedback shift registers Algorithm design and analysis Logic design Web and internet services
Content Type	Text
Resource Type	Article

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