NDLI: High level synthesis in DSP ASIC optimization

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High level synthesis in DSP ASIC optimization

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Exploring ASIC design space at system level with a neural network estimator

Structure exploration in high-level language description for logic synthesis

Scheduling in the presence of conditional constructs and optimisation of control structure

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High level synthesis in DSP ASIC optimization

Content Provider	IEEE Xplore Digital Library
Author	Isoaho, J. Oberg, J. Hemani, A. Tenhunen, H.
Copyright Year	1994
Description	Author affiliation: Signal Process. Lab., Tampere Univ. of Technol., Finland (Isoaho, J.)
Abstract	In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples.<>
Starting Page	75
Ending Page	78
File Size	342087
Page Count	4
File Format	PDF
ISBN	0780320204
DOI	10.1109/ASIC.1994.404605
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Digital signal processing Application specific integrated circuits Finite impulse response filter Quantization Logic Process design Signal processing algorithms Field programmable gate arrays Design optimization
Content Type	Text
Resource Type	Article

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